Why do the GTS HDMI FPGA IP, GTS SDI II FPGA IP, and GTS DisplayPort PHY FPGA IP fail during compilation when multiple Dual Simplex Groups are combined in to a single Dual Simplex Group but there is no error/warning shown?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, when using the Agilex™ 5 devices with multiple Dual Simplex Groups combined into a single Dual Simplex Group, a compilation error will occur without any error/warning message in the Dual Simplex assignment editor.

It is recommended to separate the arrangement based on multiple Dual Simplex Groups and not combine in single Dual Simplex Group.

Manually check and rearrange the Dual Simplex Groups accordingly if the compilation fails.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.