Article ID: 000099391 Content Type: Errata Last Reviewed: 08/02/2024

Why is link up error seen in simulation using the F-Tile Ethernet FPGA Hard IP when it is being used in the MACsec FPGA IP System Example Design?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and 24.2, the F-Tile Ethernet FPGA Hard IP shows link up error causing the transmitter reset to acknowledge and transmitter lanes stability to fail.  

    This problem is seen in designs that are custom made as in the MACsec FPGA IP System Example Design. 

     

     

    Resolution

    This problem is scheduled to be fixed in a future release of the Quartus Prime Pro Edition Software. 

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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