Article ID: 000099391 Content Type: Errata Last Reviewed: 06/13/2025

Why is a link-up error seen in simulation using the F-Tile Ethernet FPGA Hard IP when used in the MACsec FPGA IP System Example Design?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Quartus® Prime Pro Edition Software versions 24.1 and 24.2, the F-Tile Ethernet FPGA Hard IP shows a link-up error, causing the transmitter reset to acknowledge and transmitter lanes stability to fail.  

This problem is seen in designs that are custom made as in the MACsec FPGA IP System Example Design. 

 

 

Resolution

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3. 

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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