Why does the simulation of the GTS Ethernet FPGA Hard IP for the Agilex™ 5 FPGA E-Series Device (Group A), when using System PLL in custom mode, fail with the Quartus® Prime Pro Edition Software version 24.2?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, the simulation of the GTS Ethernet FPGA Hard IP for the Agilex™ 5 FPGA E-Series Device (Group A) when using System PLL in custom mode fails under the conditions below.

• Using System PLL in custom mode
• Reference clock frequency of the GTS Ethernet FPGA Hard IP is 322.265625 MHz
• Output clock frequency of the GTS Ethernet FPGA Hard IP is configured to 937.5 MHz

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.