Why does the GTS Serial Lite IV FPGA IP Design with 16 Gbps PMA data rate fail simulation when the PMA reference clock frequency is set to 160 MHz?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you might observe the GTS Serial Lite IV FPGA IP Design fails simulation while passing the hardware testing for the following configurations:

• PMA data rate: 16 Gbps
• PMA reference clock frequency: 160 MHz

To work around this problem, you can choose a different reference clock frequency, for example:  {100, 125, 200, 240, 250, 300, 320, 375} MHz.

This problem will be fixed in a future release of the Quartus® Prime Pro Edition Software.