Article ID: 000099253 Content Type: Troubleshooting Last Reviewed: 07/16/2024

Why do I see different HPS IO hashes on SDM-based FPGA designs with HPS First boot mode where the HPS EMIF IP is not instantiated?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Quartus® Prime Pro Edition Software version 24.1 and eariler, the HPS IO hash generated for Phase 1 and Phase 2 bitstreams may change between builds if the HPS EMIF is not instantiated in an HPS enabled design. This affects designs where boot mode is set to 'HPS First'.

     

     

    Resolution

    You may use the QSF assignment to avoid this problem : 

    set_global_assignment -name INI_VARS "asm_constant_hpsio_hash = on"

    This is scheduled to be fixed in a future release of Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 2 products

    Intel Agilex® 7 FPGAs and SoC FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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