Error(13224): Verilog HDL or VHDL error at altera_merlin_burst_adapter_13_1.sv(971): index 11 is out of range [10:0] for 'd0_int_nxt_addr'

Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier. You will see the error shown above when the Address Width is set to less than the correct minimum address width requirement in the AXI Bridge FPGA IP. The error will be  seen during the Quartus® Prime Pro Analysis and Synthesis stage.

To work around this problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, follow the steps below:

1. Double-click AXI Bridge FPGA IP in Platform Designer.
2. Increase the Address Width in the Bridge Parameters for the AXI Bridge FPGA IP.
3. Click the Generate HDL button.
4. Save changes before refresh.
5. Re-run the Analysis & Synthesis stage in the Quartus® Prime Pro Edition Software.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.