Article ID: 000099127 Content Type: Error Messages Last Reviewed: 07/16/2024

Why are there recovery timing violations on the External Memory Interfaces Stratix® 10 FPGA IP for DDR4 reset_sync_pri_sdc_anchor signal?

Environment

    Intel® Quartus® Prime Pro Edition
    External Memory Interfaces Intel® Stratix® 10 FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You might see recovery violations on the reset_sync_pri_sdc_anchor signal due to the automatic global promotion of this reset.

Resolution

To avoid the violations, apply the following assignment to prevent the signal from being promoted onto a global network:

set_instance_assignment -name GLOBAL_SIGNAL OFF -to <hierarchy>|reset_sync_pri_sdc_anchor

Related Products

This article applies to 1 products

Intel® Stratix® 10 FPGAs and SoC FPGAs

1