Article ID: 000099103 Content Type: Error Messages Last Reviewed: 06/13/2024

Error(11193): Output port "OUTCLK[<number>]" of "CMU_FPLL" cannot connect to PLD port "I[<number>]" of "IO_OUTPUT_BUFFER" for node "<pin name>".

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Quartus® Prime Pro Edition Software versions 22.3 to 23.3, you will see this error when a clock output of an FPLL is connected to an output pin using  2.5 V, 3.0-V LVTTL or 3.0-V LVCMOS I/O standards in Arria® 10 and Cyclone® 10 GX devices.

    Resolution

    This problem has been fixed starting from Quartus® Prime Pro Edition software version 23.4

    Related Products

    This article applies to 2 products

    Intel® Cyclone® 10 GX FPGA
    Intel® Arria® 10 FPGAs and SoC FPGAs

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