Why doesn’t ss_cold_rst_ack_n assert within 1ms of asserting ss_cold_rst_n for a mix of AN/LT and non-AN/LT configurations in the Ethernet Subsystem FPGA IP, F-Tile variant simulation with the Quartus® Prime Pro Edition Software version 24.1?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, for configurations involving a mix of ANLT and non-ANLT topology (e.g. Port0 - 100G_4 (AN = 1), Port4 - 10G_1 (AN = 0), Port5 - 25G_1 (AN = 1), etc.), when ss_cold_rst_n is asserted, ss_cold_rst_ack_n does not assert even after 1ms in the Ethernet Subsystem FPGA IP simulation. This occurs despite the INTC_SIM_AN_LT_ENABLE switch being defined, as the firmware version (fw_version) is not properly loaded. 

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.