Why does Multi Channel DMA FPGA IP for PCI Express* of H-Tile significantly drop packets when running Avalon-ST Packet Generate/Check Design Example?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you might observe that TLP packets are dropped significantly when running Avalon-ST Packet Generate/Check Design Example of Multi Channel DMA FPGA IP for PCI Express*  for H-Tile if the payload size is set as 64/128 bytes per descriptor.

To work around this problem, set payload size larger than 128 bytes for DMA transfer in the commmand when running the test as following for the -p option.

./perfq_app -b 0000:98:00.0 -p 256 -d 1 -c 8 -a 8 -l 25 -z -n

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.