Article ID: 000098888 Content Type: Errata Last Reviewed: 05/20/2024

Why does the MAC TX of the F-Tile Ethernet FPGA Hard IP halt its transmission of control frames (0x8808) upon receiving PAUSE frames from the link partner?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    According to Annex 31B.1 of the IEEE802.3 specification, it is noted that the pause operation does not inhibit the transmission of MAC control frames. However, the current implementation of the F-Tile Ethernet FPGA Hard IP mechanism for handling Ethernet frames is not aligned with this specification, as we pause the transmission of all Ethernet frames indiscriminately, regardless of their type. 

    Users wishing to transmit PFC or SFC frames can utilize the SFC/PFC frame generation within HIP, facilitated by register configuration. It's important to note that while our system supports these specific frames, the IEEE specification includes a broader range of control frame types, as outlined in Annex 31A, which HIP does not generate. 

    Alternatively, customers can configure the F-Tile Ethernet FPGA Hard IP to not halt traffic transmission upon receiving Pause frames. Instead, they can utilize the o_pause signal to make transmission decisions at the user end, particularly regarding the transmission of any control frames. 

    Resolution

    There is no workaround for this problem.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs