Article ID: 000098872 Content Type: Errata Last Reviewed: 05/27/2024

Why is the Fronthaul Compression FPGA IP Example Design unable to meet timing requirements, especially with the Stratix® 10 H-Tile?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you may see a timing failure when the Data Direction is set to "TX and RX" and the Compression Method is set to "BFP". 

     

    Resolution

    This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 5 products

    Intel® Stratix® 10 GX FPGA
    Intel® Stratix® 10 MX FPGA
    Intel® Stratix® 10 NX FPGA
    Intel® Stratix® 10 SX SoC FPGA
    Intel® Stratix® 10 TX FPGA

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