Article ID: 000098851 Content Type: Errata Last Reviewed: 12/07/2024

Why does the simulation with negative polarity inversion enable PASS in the F-Tile Ethernet Intel® FPGA Hard IP?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, it is found that, when interface attributes settings for negative polarity inversion, i.e “tx_invert_p_and_n=ENABLE” and “rx_invert_p_and_n=DISABLE”, or “tx_invert_p_and_n=ENABLE” and “rx_invert_p_and_n=DISABLE” is set the simulation will PASS in contrary to expected behavior.

Resolution

There is currently no workaround for this problem.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.
 

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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