Why does the high-voltage I/O (HVIO) input pin stuck at high in Agilex™ 5 FPGA devices?

Due to a problem in Quartus® Prime Pro Edition Software version 23.4.0 Patch 009, 23.4.1, and 24.1, you may observe HVIO input pin stuck at high in Agilex™ 5 FPGA if the design doesn’t include a transceiver and RCOMP pin left unconnected while the HVIO pin is configured as input or bidirectional. This issue does not affect the device configuration process and the device can enter user mode.

A patch is available to fix this problem for Quartus® Prime Pro Edition Software version 24.1. Download and install patch 0.15fw from the appropriate attachment below.

• Download patch for Windows quartus-24.1-0.15fw-windows (.exe)
• Download patch for Linux quartus-24.1-0.15fw-linux (.run)
• Download the Readme for patch 0.15fw quartus-24.1-0.15fw-readme (.txt)

This problem is planned to be fixed in a future release of Quartus® Prime Pro Edition Software.