Article ID: 000098803 Content Type: Errata Last Reviewed: 05/08/2024

Why is the Function Level Reset request being ignored or not processed by the GTS AXI Streaming FPGA IP for PCI Express*?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, back-to-back Function Level Reset requests with intervals less than 16 axi_st_clk clock cycles may not be handled correctly by the GTS AXI Streaming FPGA IP for PCI Express*.

    Resolution

    This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

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