Why does GTS AXI Streaming FPGA IP for PCI Express* fail to link up in the simulation with Synopsys VIP?

Due to a problem in the Quartus® Prime Pro Edition Software version 23.4 and onward, you may observe PCIe link-up failure in the GTS AXI Streaming FPGA IP for PCI Express* simulation with Synopsys VIP.

To work around this problem, bypass EQ phase 2 and phase 3 by setting “1” to the following 2 registers in the testbench.

• intel_pcie_gts_inst.gen_sm_qhip.u_sm_qhip.sm_pcie_hal_top_inst.pcie_hal_top.pcie_phip_hal_ctrltop_x4.pcie_phip_hal_ctrltop.phip_pcie_ctrltop_x4.sf_rtl_ncrypt_inst.sf_rtl_inst.u_core4.u_ip.u_dwc.u_DWC_pcie_core.u_cx_pl.u_smlh.u_smlh_ltssm.cfg_gen3_eq_phase23_disable  
• intel_pcie_gts_inst.gen_sm_qhip.u_sm_qhip.sm_pcie_hal_top_inst.pcie_hal_top.pcie_phip_hal_ctrltop_x4.pcie_phip_hal_ctrltop.phip_pcie_ctrltop_x4.sf_rtl_ncrypt_inst.sf_rtl_inst.u_core4.u_ip.u_dwc.u_DWC_pcie_core.u_cx_pl.u_smlh.u_smlh_ltssm.cfg_gen4_eq_phase23_disable 

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.