Due to a problem in Quartus® Prime Pro Edition and Standard Edition version 22.1 and later, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device.
Prior to version 22.1, the initial state of DATA[3:2] was high. However, starting from version 22.1 and later, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. Some variants of Quad SPI flash memory devices have reset or hold function on DATA[3] and write protect function on DATA[2]. When using one of those variant, DATA[3:2] may be recognized as low and reset, hold, or write protect function may be unexpectedly enabled. This results in failure to access the QSPI flash memory device.
DATA pins are called DATA, DQ, IO, or SIO depending on the QSPI flash memory device vendor.
DATA[3:2] must be kept high as the initial state. Use one of the following workarounds.
- Add external pull-up registers to the I/O VCC voltage on DATA[3:2]
- Enable internal weak pull-up register on DATA[3:2] pins in your Quartus® design project
When the ASMI block is used and DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins, use the workaround #1 because internal weak pull-up resister option is unavailable.
This problem is scheduled to be fixed in a future release of the Quartus® Prime Software.