Article ID: 000098741 Content Type: Troubleshooting Last Reviewed: 05/08/2024

Why does the F-Tile Serial Lite IV Toolkit fail to enable Internal Serial Loopback during Link Initialization?

Environment

  • Intel® Quartus® Prime Pro Edition
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    Description

    There is a problem with the F-Tile Serial Lite IV Toolkit where internal serial loopback enablement is unsuccessful and outputs incorrect register value when performing Link Initialization. It's due to we internally changed to demo_jtag when checking tx_pll_locked and rx_cdr_locked status during system-reset proc. But didn't change it back to phy_jtag when completed. 

     

    Resolution

    To work around this problem, you need to follow below steps:

    1. Click "Assert system Reset"
    2. Click "Deassert system Reset"
    3. Go to GUI Configuration tab and set JTAG to phy_jtag_m.master
    4. Click "Link Initialization"

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs