Article ID: 000098734 Content Type: Troubleshooting Last Reviewed: 04/25/2024

Why does the F-Tile PMA/FEC Direct PHY FPGA IP variant fail Quartus® Support Logic Generation with Enable TX double width transfer and Enable RX double width transfer parameters selected and the RX core interface FIFO mode option is set to Elastic?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, the F-Tile PMA/FEC Direct PHY FPGA IP will fail to pass Quartus® Support Logic Generation when the Enable TX double width transfer and Enable RX double width transfer parameters are selected, and the RX core interface FIFO mode option is set to Elastic?

    Resolution

    There is no workaround for this problem.

    This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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