This error message might be seen during the Analysis & Synthesis stage when migrating a design containing Serial Flash Loader FPGA IP from Quartus™ Prime Standard Edition Software version 20.1 and earlier to a newer version of the Quartus™  Prime Standard Edition Software. This is because the code changes in the generated Verilog HDL design file (alt_sfl_enhanced.v) of the Serial Flash Loader FPGA IP require the altclkctrl module to be instantiated in the design.

To work around this problem, use one of the following steps:

•   Upgrade the Serial Flash Loader FPGA IP using the "Upgrade IP Components" feature.

Or

•   Instantiate and add the ALTCLKCTRL FPGA IP in the design.