Due to the current specifications, a DCFIFO IP may output unexpected control signals during reset using aclr signal. For example, when the rdempty signal indicates high for empty right before resetting a DCFIFO IP, rdempty may asynchronously output low for a moment during reset, and then go back to high.
As the notes 22 and 24 say in 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect of FIFO IP User Guide, even though the aclr signal is synchronized with the write clock or the read clock, asserting the aclr signal still affects all the status flags asynchronously. The status flags means empty, wrempty, rdempty, full, wrfull, rdfull, usedw, wrusedw, and rdusedw. Because those signals are output from combinational logic, resetting the IP may cause glitches on those signals. Your user logic connected to the DCFIFO may receive unexpected statuses during the reset operation.
Design your user logic connected to the DCFIFO IP, considering a case where the DCFIFO outputs unexpected status signals asynchronously during reset.
For example, you can add registers to the status signals and reset the registers during reset operation to avoid receiving unexpected statuses.