Why does the QSF assignment get re-ordered after the IP upgrade in the Quartus® Prime Pro Edition Software version 24.1?

As FPGA Intellectual Property (IP) solutions have replaced Nios® V Processor for FPGA for Nios II Processor for FGPA from the Quartus® Prime Pro Edition Software version 24.1, you may encounter that the QSF assignments in your project could be re-ordered after an IP upgrade to the Quartus® Prime Pro Edition Software version 24.1 resulting in a timing violation after the upgrade. 

List of IPs affected:

1. H-tile Hard IP Ethernet Intel FPGA IP (Example Design)
2. E-tile Hard IP Ethernet Intel FPGA IP (Example Design)
3. E-tile Hard IP Agilex™ 7 Design Example
4. F-tile Dynamic Reconfiguration Suite FPGA IP
5. Low Latency 100G Ethernet Stratix® 10 FPGA IP
6. 25G Ethernet Stratix® 10 FPGA IP
7. Low Latency E-tile 40G Ethernet FPGA IP
8. Low Latency 50G Ethernet FPGA IP Design Example (Stratix® 10 Device)
9. Stratix® 10 10GBASE-KR PHY IP
10. E-tile Dynamic Reconfiguration FPGA IP Design Example
11. Stratix® 10 10GBASE-KR PHY IP
12. Ethernet Subsystem FPGA IP
13. Arria® 10 Transceiver Native PHY
14. SDI II FPGA IP (Applicable only to Design Example)
15. HDMI FPGA IP (Applicable only to Design Example)
16. DisplayPort FPGA IP (Applicable only to Design Example)
17. F-tile included in the design

A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1.
Download and install Patch 0.14 from the appropriate link below.

• Download patch 0.14 for Windows (quartus-24.1-0.14-windows.exe)
• Download patch 0.14  for Linux  (quartus-24.1-0.14-linux.run)
• Download the Readme for patch 0.14 (quartus-24.1-0.14-readme.txt)

This problem is fixed beginning with the Quartus Prime Pro Edition software version 24.2.