In Quartus® Prime Pro Edition Software version 24.1, when running the Performance Monitor in the HBM2E IP example design, the Test Engine IP sets the address to 16 bits. By controlling only 16 bits, we only randomize bits [21:6] or [22:7] (depending on AXI4 interface width) of the address. The performance captured in the reduced number of randomized bits, which is less than the full bus, does not represent the actual performance of the full bus.
This issue is purely related to the Test Engine IP within the HBM2E IP example design, and this issue does not occur with the stand-alone version of the HBM2E IP.
After generating the HBM2E IP example design, open the ed_synth.qsys file in Platform Designer, select the Test Engine IP component and Modify the "Address ALU argument width" parameter to 32 bits for each driver you are interested in measuring performance.
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software