Why do I get timing closure failures when compiling the LPDDR5 EMIF Example Design for the Agilex™ 7 M Series or the Agilex™ 5 FPGAs?

In Quartus® Prime Pro Edition Software version 24.1, when compiling the LPDDR5 EMIF Example Design for either the Agilex™ 7 M Series or the Agilex™ 5 FPGAs, you will encounter the following Design Assistant Violations:

CDC-50012 - Multiple Clock Domains Driving a Synchronizer Chain

TMC-20027 - Collection Filter Matching Multiple Types 

These violations result in timing closure failures seen in the Timing Analyzer.

The timing closure failures which result from these Design Assistant Violations can be ignored and will be updated in a later release of Quartus®.