Article ID: 000098682 Content Type: Troubleshooting Last Reviewed: 11/18/2024

Why is it hung when I poll o_tx_hip_ready for assertion in the GTS CPRI PHY FPGA IP with the Agilex™ 5 device ?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The o_tx_hip_ready port is exposed in the GTS CPRI PHY FPGA IP but it’s not used. If you poll o_tx_hip_ready port for status check, the assertion will never happen. 

     

    Resolution

    This problem is fixed beginning with the Quartus Prime Pro Edition Software version 24.2.

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