For a PCIe link in a transceiver bank, there are two pins in HVIO banks with optional function as pin perst for the PCIe link.
You can connect PERST# to either one of the reset pins. For the reset pin not used as PERST#, it can be used as a generic HVIO signal.
For example, if pin PIN_PERST_N_CVP_L1A_0 in Bank 5A is assigned as PERST# for the PCIe link in Bank L1A, pin PIN_PERST_N_CVP_L1A_1 in Bank 5B can be assigned as a generic HVIO signal.
Due to a problem in the ES devices, assigning any of the two reset pins as PERST# fails to reset the PCIe link.
To work around this problem, connect the PERST# to the i_gpio_perst0_n port of the GTS AXI Streaming FPGA IP for PCI Express, tie the p0_pin_perst_n_i port to logic high. Assign the i_gpio_perst0_n port to either one of the reset pins location in the corresponding HVIO bank. The other reset pins not used as PERST# can be connected as a generic HVIO signal. The i_gpio_perst0_n only releases PCIe HIP and GTS transceiver from reset after FPGA enters user mode. Hence CvP is not supported and may not reach Gen 1/2 L0 state within 100ms after PERST# deactivation during cold reset.
In a future release of Quartus Prime Pro Edtion software, you can connect PERST# to the p0_pin_perst_n_i port (assign to one of the reset pins locations in the HVIO bank). However, the other reset pin in HVIO cannot be connected on PCB. These limitations will be fixed in production devices.