Why is the TXPLL or CDR unable to achieve lock to reference clock for Agilex™ 5 FPGA designs, which have GTS transceivers and HPS EMIF enabled when using bitstream compiled and generated in the Quartus® Prime Pro Edition Software version 23.4.1 and 24.1?

In the Agilex™ 5 FPGA designs, which enable HPS EMIF and IPs using GTS transceivers, the TX PLL or CDR of the GTS transceiver will not be able to lock to its reference clock. This is due to a problem in the Quartus® Prime Pro Edition Software versions 23.4.1 and 24.1, which incorrectly sets the reference clock mux. In designs with IPs using GTS transceivers only without HPS EMIF enabled, the GTS transceiver TX PLL or CDR can achieve lock to the reference clock.

A patch is available to fix this problem for the Quartus® Prime Pro Edition Software version 24.1.  Download and install Patch 0.08 from the appropriate link below.

• Download patch 0.08 for Windows (quartus-24.1-0.08-windows.exe)
• Download patch 0.08  for Linux  (quartus-24.1-0.08-linux.run)
• Download the Readme for patch 0.08 (quartus-24.1-0.08-readme.txt)

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.