Article ID: 000098667 Content Type: Troubleshooting Last Reviewed: 04/24/2024

Why does the IO Bank Usage report in Quartus® Prime Pro Edition Software show that a VREF is required for banks that contain Differential SSTL/HSTL inputs when using Stratix® 10 devices?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in Quartus® Prime Pro Edition Software version 24.1 and earlier when using Stratix® 10 devices, the IO Bank usage shows a VREF is required for banks that contain Differential SSTL/HSTL inputs but no single ended SSTL/HSTL inputs. 

     

    Resolution

    Differential SSTL/HSTL inputs do not require an external VREF, so you can ignore this for banks with Differential SSTL/HSTL inputs and no single ended SSTL/HSTL inputs.

    This issue will be fixed in a future version of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel® Stratix® 10 FPGAs and SoC FPGAs

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