Article ID: 000098665 Content Type: Troubleshooting Last Reviewed: 05/21/2025

Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction?

Environment

    Intel® Quartus® Prime Standard Edition
    ALTLVDS_RX
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see that the input register is not registered in the ALTLVDS_RX megafunction's negative input pins, rx_in[*](n).

This is because the synthesis attributes "LVDS_RX_REGISTER=LOW" and "LVDS_RX_REGISTER=HIGH" are not assigned to the register in the Low-voltage differential signaling (LVDS) receiver interfaces.

Resolution

To work around the problem, add the following assignments in the Quartus® Settings File (.qsf):

set_instance_assignment -name LVDS_RX_REGISTER LOW -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_l_reg"
set_instance_assignment -name LVDS_RX_REGISTER HIGH -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_h_reg"

This problem is currently scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software. 

Related Products

This article applies to 11 products

Intel® Cyclone® 10 LP FPGA
MAX® V CPLDs
Arria® V GZ FPGA
Cyclone® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
MAX® II CPLDs
Arria® II FPGAs
Cyclone® IV FPGAs
Intel® MAX® 10 FPGAs
Stratix® V FPGAs

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