Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the Design Assistant Timing Closure Summary flags the Agilex™ 5 MIPI D-PHY FPGA IP as high with warning messages as shown below for certain reference clock frequency and operating bit rate combinations.
Warning(332060): Node: dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst~ncntr_reg was determined to be a clock but was found without an associated clock assignment.
Info(13166): Register dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst~mcntr_reg is being clocked by dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst~ncntr_reg
Warning(332060): Node: dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst~c0cntr_reg was determined to be a clock but was found without an associated clock assignment.
Info(13166): Node dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst|out_clk_periph0 is being clocked by dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst~c0cntr_reg
Warning(332060): Node: dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst~c1cntr_reg was determined to be a clock but was found without an associated clock assignment.
Info(13166): Node dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst|out_clk_periph1 is being clocked by dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst~c1cntr_reg
Warning(332088): No paths exist between clock target "dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst|out_clk_periph0" of clock "mipi_u0_PHY_CLK_0" and its clock source. Assuming zero source clock latency.
Warning(332088): No paths exist between clock target "dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst|out_clk_periph1" of clock "mipi_u0_PHY_CLK_SYNC_0" and its clock source. Assuming zero source clock latency.
Warning(332088): No paths exist between clock target "dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst|vco_clk_periph" of clock "mipi_u0_PLL_VCO_CLK_0" and its clock source. Assuming zero source clock latency.
Warning(332088): No paths exist between clock target "dut|dphy|dphy|arch|dphy_inst|dphy_core_inst|clk_rst|pll_gen[0].iopll_wrap_inst|iopll_inst|vco_clk[0]" of clock "mipi_u0_PLL_VCO_CPA_CLK_0" and its clock source. Assuming zero source clock latency.
These Design Assistant Summary warnings do not affect the overall Quartus® Prime Pro Edition Software timing analysis, as the path delay is common to both the Launch and Latch Clock Paths.
There is no workaround in Quartus® Prime Pro Edition Software version 24.1.
This problem has been fixed in 24.3 version of the Quartus® Prime Pro Edition Software.