Why do I see unexpected throughput results when running the F-Tile Triple-Speed Ethernet FPGA IP Design Example?

Due to an issue in Quartus® Prime Pro Edition Software version 24.1, the F-Tile Triple-Speed Ethernet FPGA IP Design Example for the 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver variant, the ff_tx_clk and ff_rx_clk must be set to 100 MHz for 32 bits FIFO. Still, this update has not been reflected in the TCL scripts used for throughput calculation. Consequently, unexpected throughput calculation discrepancies may occur when running the F-Tile Triple-Speed Ethernet FPGA IP Design Example for the 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with F-Tile FGT Transceiver variant.

To work around this problem in version 24.1 of the Quartus® Prime Pro Edition Software, perform the following steps:

1. Goto the directory <design example project directory>/hardware_test_design/hwtest/agx/2xtbi_pma/traffic_controller/mon
2. Open the file mon_inc.tcl in a suitable text editor.
3. Change the following line[Line 90] in the tcl file.

              FROM:

set THRUPUT   [format %2.2f [expr {1.25*$SUMBYTES/$SUMCYCLES}]]

             TO:

set THRUPUT   [format %2.2f [expr {1.00*$SUMBYTES/$SUMCYCLES}]]

        4. Save the file.

5. Run the design example in hardware using the modified script files in System Console.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.