Article ID: 000098581 Content Type: Error Messages Last Reviewed: 11/22/2024

Internal Error: Sub-system: U2B2_CORE, File: /quartus/db/u2b2/u2b2_2wt_util.cpp, Line: 18

Environment

Intel® Quartus® Prime Pro Edition software version 23.4.1 and version 24.1

  • Intel® Quartus® Prime Pro Edition
  • Native Fixed Point DSP Intel® Cyclone® 10 GX FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.4.1 and version 24.1. You will see the Internal Error(IE) shown above when using the Primitive DSP Native Fixed Point DSP Agilex™ FPGA IP with the operation mode set to m18x18_full and the Enable 'ax/bx/cx/dx/ex/fx' input register: and the Enable 'ay/by/cy/dy/ey/fy' or 'scanin' input register: options set to different values.

    An IE will be observed if these options are not set to the same value, for example, if ena0 and ena1 are used.

    All 'input registers' must be set to the same setting value.

     

    Resolution

    When the Primitive DSP Native Fixed Point DSP Agilex™ FPGA IP with the operation mode set to m18x18_full, all 'input registers' must be set to the same setting value.

    This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.