Description
You may see the fitter error messages when you compile Agilex™ 7 M-Series EMIF IP and Agilex™ 5 EMIF IP with full EMIF IP pin location assignments with Quartus® Prime Pro Edition Software versions 24.1 beyond.
Resolution
To workaround this Intel® recommends to manually constraints some interface signals and allow Quartus® fitter to place the pins. For this method of I/O placement, you must constraints the following signals
- PLL reference clock
- RZQ pin
- MEM_RESET_N