Article ID: 000098515 Content Type: Troubleshooting Last Reviewed: 04/17/2024

Why does the synchronous clear of the fast input register operate incorrectly in Arria® 10 devices?

Environment

  • Intel® Quartus® Prime Design Software
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    Description

    Due to a problem in the Quartus® Prime Software, the active state of the synchronous clear of the fast input register is the other way round in Arria® 10 devices.  For example, even though you use a fast input register with an active low synchronous clear in your design, the active state of the synchronous clear is wrongly set to high. 

    The affected software versions are as follows:

    • Quartus® Prime Pro Edition Software 22.1 and earlier
    • Quartus® Prime Standard Edition Software 23.1 and earlier
    Resolution

    This problem has been fixed in the Quartus® Prime Pro Edition Softwere version 22.2 and later.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs