The fitter error shown below will be seen when using the Quartus® Prime Pro Edition Software version 24.1 when placing the reference clock pin(s) or RZQ pin in a different sub-bank than the Agilex™ 5 MIPI D-PHY FPGA IP has been placed.
Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)). Fix the errors described in the submessages, and then rerun the Fitter. The FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 IOPLL, which is within Generic Component dphy_dut_dphy.
To workaround this problem, please set the reference clock input type to not balanced in your Quartus® Settings File (.qsf).
Shown below is an example of the required assignment for the Design Example generated by the Agilex™ 5 MIPI D-PHY FPGA IP.
set_instance_assignment -name PLL_REFCLK_INPUT_TYPE NOT_BALANCED -to *dphy_core_inst|clk_rst|pll_gen[*].iopll_wrap_inst|iopll_inst -entity ed_synth