Article ID: 000098507 Content Type: Troubleshooting Last Reviewed: 12/07/2024

Why do I see a read data mismatch in the clk_tx_div_khz register when simulating the F-Tile Ethernet FPGA Hard IP by enabling the ETH_SIM_SPEED option?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition software version 24.1, you may see a read data mismatch in clk_tx_div_khz register when simulating the F-Tile Ethernet FPGA Hard IP with enabling ETH_SIM_SPEED option. 

    This problem does not happen in simulation when the ETH_SIM_SPEED option is not enabled, and it does not happen with hardware. 

    Resolution

    This problem is scheduled to be fixed in the future release of the Quartus® Prime Pro Edition software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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