Article ID: 000098507 Content Type: Troubleshooting Last Reviewed: 06/16/2025

Why do I see a read data mismatch in the clk_tx_div_khz register when simulating the F-Tile Ethernet FPGA Hard IP by enabling the ETH_SIM_SPEED option?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Quartus® Prime Pro Edition software version 24.1, you may see a read data mismatch in the clk_tx_div_khz register when simulating the F-Tile Ethernet FPGA Hard IP with enabling ETH_SIM_SPEED option enabled. 

This problem does not occur in simulation when the ETH_SIM_SPEED option is not enabled, and does not occur with hardware. 

Resolution

This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.1.

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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