Description
Due to an unexpected behavior in the Agilex™ 7 F-tile Ethernet Intel® FPGA Hard IP 25G variant, there is a frequency mismatch between o_clk_rec_div and o_clk_revc_div64. Hence, you will observe a loss in the link for one clock cyreset sequence and before o_rx_pcs_ready is available in the Agilex™ F-Tile Ethernet Intel® FPGA Hard IP 25G variant.
Resolution
This problem is scheduled to be fixed in the future release of the Intel® Quartus® Prime Pro Edition software.