Due to a problem in the Quartus® Prime software version 23.4 and earlier, the clock multiplexing of the Clock Control FPGA IP performs incorrectly when the Number of Clock Inputs is 2.
When the Number of Clock Inputs is 2, the Clock Control FPGA IP has two clock source input ports (inclk0x and inclk1x) and an input port to select the clock source (clkselect).
The clock multiplexing of the Clock Control FPGA IP in 23.4 and earlier performs as follows:
- When clkselect=0, inclk1x is selected
- When clkselect=1, inclk0x is selected
However, it should perform as follows:
- When clkselect=0, inclk0x is selected
- When clkselect=1, inclk1x is selected
This problem affects Agilex™ 7 F-Series, I-Series, and M-Series.
To work around this problem, use the Number of Clock Inputs as 4 instead of 2, use two input clock source ports, and leave the other input clock ports unused.
When using the Number of Clock Inputs of 4, the Clock Control FPGA IP performs as expected with inclk0x, inclk1x, inclk2x, inclk3x, and clkselect[1:0] ports.
You can use the following connections, for example.
- inclk0x - Connect a clock source
- inclk1x - Connect a clock source
- inclk2x, inclk3x - Input fixed "0" or "1"
- clkselect[0] - Connect a signal to select the clock source
- clkselect[1] - Input fixed "0"
This problem will be fixed in a future version of the Quartus® Prime Software.