Article ID: 000098481 Content Type: Troubleshooting Last Reviewed: 04/02/2024

Why is link up error seen in simulation using either the F-Tile Ethernet Intel® FPGA Hard IP or the F-Tile Ethernet Multirate Intel® FPGA IP when FAST SIM switches with UX_CLOCK_DRIFT_CORRECTION macro is enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you may see link up error in simulation using either the F-Tile Ethernet Intel® FPGA Hard IP or the F-Tile Ethernet Multirate Intel® FPGA IP when FAST SIM switches with UX_CLOCK_DRIFT_CORRECTION macro is enabled.

    Resolution

    The workaround for this problem is removal of FAST SIM switches with UX_CLOCK_DRIFT_CORRECTION macro from the design. 

    This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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