Why does External Memory Interface (EMIF) calibration fail when enabling an input pin on a I/O Lane which is not used for implementing fabric EMIF on Agilex™ 7 FPGA and Agilex™ 5 FPGA?

Due to an issue in the Quartus® Prime Pro Edition Software version 24.1 and earlier, you will encounter EMIF calibration failure on Agilex™ 7 FPGA M-Series and Agilex™ 5 FPGA E-Series devices when both the conditions below are met:

• User enable input pin using non-LVCMOS I/O Standard on an I/O Lane that is not used for EMIF purposes.
• The I/O Lane resides in the same HSIO bank used to implement fabric EMIF.

The work around is available for Agilex™ 7 FPGA M-Series and Agilex™ 5 FPGA E-Series devices to resolve this issue, do not enable input pin with the affected I/O standard on the specific I/O Lane.

Also  patch is available  to resolves the issue for  Agilex™ 5 FPGA E-Series devices Click here to download for Quartus® Prime Pro Edition Software version 24.1.

This issue will be fixed in a future Quartus® Prime Software version.