Article ID: 000098422 Content Type: Errata Last Reviewed: 06/16/2025

Why does the Cadence Xcelium* simulator fail when using Dynamic Reconfiguration IP with PTP?

Environment

    Intel® Quartus® Prime Pro Edition
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Description

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, Agilex™ 7 F-Tile Dynamic reconfiguration IPs with PTP may show errors when using the Cadence Xcelium* simulator, similar to the error shown below: 

xmelab: *E,CUVIMG (../hardware_test_design/support_logic/eth_f_hw_auto_tiles.sv,23321|341): Implicit name not allowed in hierarchical name.

 

Resolution

There is no workaround.
 

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

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