Why is the clock frequency of *usr_clk different when multiple instances of PHY Lite for Parallel Interfaces FPGA IP are implemented

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and earlier, the clock frequency of *usr_clk when multiple instances of the PHY Lite for Parallel Interfaces Agilex™ 7 FPGA IP are implemented is incorrect, which causes the incorrect timing analysis result.

To work around this problem, perform the following steps:

1. Open *pin_map.tcl under .../synth folder

2.  Modify the following command:

set pins(pll_ref_clock) $pll_ref_clock

to 

set pins(pll_ref_clock) [get_pins -no_duplicates $pll_ref_clock]

This problem has been fixed starting in version 23.4 of Quartus® Prime Pro Edition Software.