Description
Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, you might see this error message when you have a Verilog/System Verilog HDL file that maps input ports to values with direct decimal. For example: .input_signal ( 1 ).
Resolution
To work around this problem, change the direct decimal value to 'base<value> syntax. For example: change .input_signal ( 1 ) to .input_signal ( 'b1 ).