Article ID: 000098407 Content Type: Troubleshooting Last Reviewed: 11/12/2024

Why do I measure high jitter on the “rx_clkout” pin of the F-Tile PMA/FEC Direct PHY FPGA IP or F-Tile PMA/FEC Direct Multirate FPGA IP variant?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Pro Edition Software version 23.4, higher than expected jitter may be measured on the rx_clkout pin of the F-Tile PMA/FEC Direct PHY FPGA IP or the F-Tile PMA/FEC Direct Multirate FPGA IP cores when the CDR is set to lock-to-reference mode.

     

     

    Resolution

    There is no workaround for this problem.

    This problem has been fixed in version 24.2 of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs

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