Article ID: 000098395 Content Type: Product Information & Documentation Last Reviewed: 03/25/2024

Why does the calculated VCO frequency of TX FGT PLL fractional mode in the IP Catalog GUI mismatch with the VCO frequency formula in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide?

Environment

  • Intel® Quartus® Prime Pro Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to incorrect formula in the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide (UG20315), you may see the calculated VCO frequency of TX FGT PLL fractional mode in the IP Catalog GUI when Enable TX FGT PLL fractional mode option enabled mismatch the VCO frequency calculated by the formula in F-Tile Architecture and PMA and FEC Direct PHY IP User Guide with M,K,N,L and reference clock frequency parameters which reported in system messages window. 

     

    The correct formula is the following:

     

    VCO frequency = (M + k/2^22) * refclk frequency (MHz) * mul_div / N.

     

     

    Resolution

    This problem is currently scheduled to be resolved in a future release of the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide (UG20315).

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs