Article ID: 000098232 Content Type: Troubleshooting Last Reviewed: 03/25/2024

When performing Link Disable-Enable loop testing with the R-Tile Avalon® Streaming FPGA IP for PCI Express*, why does the host system report Polling.Active timeout failures?

Environment

  • Intel® Quartus® Prime Pro Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the R-Tile Avalon® Streaming FPGA IP for PCI Express*, Host systems may report Polling.Active timeout failures when running LTSSM Link disable-enable loop tests. This failure is limited to Port 0 of the R-Tile Avalon® Streaming FPGA IP for PCI Express*.

     

    Resolution

    This problem has no functional implication, and is not planned to be fixed in a future version of the Quartus® Prime Pro Edition Software.

    Related Products

    This article applies to 1 products

    Intel Agilex® 7 FPGAs and SoC FPGAs I-Series

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