Why does the E-Tile Ethernet IP for Agilex™ 7 FPGA Design Example generate errors during compilation?

Due to a problem in the Quartus® Prime Pro Edition Software v23.2, compilation failure will happen after generating the E-tile Ethernet IP for Agilex™ 7 FPGA Design Example with the following options:

1. set Core Variant to any option other than Dynamic Reconfiguration;
2. check the enable ANLT checkbox;
3. set Core Variant to Dynamic Reconfiguration;
4. generate the Design Example;

The compilation will fail with the following error messages:

Error(13264): Can't resolve multiple constant drivers for net "sl_csr_rst_dr_cpu[3]" at ex_100G_alt_ehipc3_fm_2410_zfihiqq.sv(2284)

Error(13265): Constant driver at ex_100G_alt_ehipc3_fm_2410_zfihiqq.sv(3715)

Error(16186): Can't elaborate top-level user hierarchy

Error: Flow failed: ERROR: Elaboration Failed for Partition(s) "|"

To work around this problem, ensure that enable ANLT is not set before setting Core Variant to Dynamic Reconfiguration, and then generate example design.

The options enable ANLT and Dynamic Reconfiguration are mutually exclusive and should not be enabled at the same time.

This problem has been fixed in Quartus® Prime Pro Edition Software version 24.1.