Article ID: 000098201 Content Type: Troubleshooting Last Reviewed: 11/22/2024

Why does the 2D-FIR II (4K ready) FPGA IP core return unexpected data between two output samples in simulation when using the SIEMENS* QuestaSim*?

Environment

    Intel® Quartus® Prime Design Software
    2D-FIR II (4K ready) Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem with the encryption of the 2D-FIR II (4K ready) FPGA IP simulation files for the SIEMENS* QuestaSim*,  unknown data will be seen between two consecutive output data when simulating the 2D-FIR II (4K ready) FPGA IP.

This issue does not affect the operation in hardware.

 

 

Resolution

No workaround for this simulation problem exists.

This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro Edition Software.

Related Products

This article applies to 11 products

Intel Agilex® 7 FPGAs and SoC FPGAs
Arria® II FPGAs
Arria® V FPGAs and SoC FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
Cyclone® IV FPGAs
Cyclone® V FPGAs and SoC FPGAs
Intel® Cyclone® 10 FPGAs
Intel® MAX® 10 FPGAs
Intel® Stratix® 10 FPGAs and SoC FPGAs
Stratix® IV FPGAs
Stratix® V FPGAs

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