How to compile the discontinued Nios® II processor IP core in future Quartus® Prime Software?

The discontinued Nios® II processor IP core is rendered unavailable in the Quartus® Prime IP Catalog after Last Time Shipments. Interested parties are encouraged to refer to the  Nios® II Processor Product Discontinuation Notice (PDN2312).

The recommended action is to implement Nios® V processor IP with equivalent functions in new designs. Alternatively, the discontinued Nios® II processor IP core supports design compilation with pre-generated IP files.

On the Nios® II hardware flow: 

In the last Quartus® Prime Software version (that supports Nios® II processor IP core),

• Open the Platform Designer system.
• Click Generate HDL.
• Convert the Nios® II processor IP Core into a generic component.
  1. Select the processor.
  2. Navigate to the Component Instantiation tab.
  3. Select Implementation Type as Blackbox.
  4. Click Apply.
• Save the Platform Designer system

.

The system is ready for regeneration and recompilation in the latest or future Quartus® Prime Software (that does not support Nios® II Processor IP core).

Note: Nios® II processor license is required in the Quartus® Prime software. 

On the Nios® II software flow:

Nios® II Software Build Tools for Eclipse are last supported in,

• Quartus® Prime Pro Edition Software version 23.4, and
• Quartus® Prime Standard Edition Software version 23.1.

Users must continue Nios® II software development (Nios® II Board Support Package and Application projects) in these software versions or earlier.

Please take a look at the requirements and limitations to implement the workaround.

You are required to,

• Preserve the Nios® II processor .ip file and its generated RTL folder (it should have the same name as the Nios® II processor .ip file).
• Preserve the SOPCINFO file.
• Configure the Quartus® Prime Software.

         Navigate to Assignment > Settings > Board and IP Settings > IP regeneration policy, select Never regenerate design files for IP cores.

                                ​
 

         Upon Generating HDL, disable Clear output directories for selected generation targets in Generation > Output Directory.

         If quartus_ipgenerate command is applied, remove --clean or –clear_ip_generation_dirs.

You are limited to,

• Fixed generic Nios® II processor component. Due to the preserved IP files, any changes made onto the Nios® II processor are not reflected.
• Fixed IP cores or connections to the Nios® II processor. This is to maintain the host-agent services between the Nios® II processor and other IP cores.
• Fixed Nios® II SOPCINFO files for BSP files generation. This is constrained by the above limitations.