Whilst not supported by Altera, the Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Design Example Testbench is in clear text RTL and can be modified to include simple additional transactions.
The testbench and Root Port BFM or Endpoint BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the variation. This BFM allows you to create and run simple task stimuli with configurable parameters to exercise basic functionality of the example design. The testbench and BFM are not intended to be a substitute for a full verification environment. Corner cases and certain traffic profile stimuli are not covered. Refer to the items listed below for further details. To ensure the best verification coverage possible, Atlera strongly suggests that you obtain commercially available PCI Express verification IP and tools, or do your own extensive hardware testing, or both.
The Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide section 13.1. Avalon-MM Endpoint Testbench incorrectly states that the file altpcietb_bfm_rp_gen3_x8.sv should be the module used to modify and vary the transactions sent to the example endpoint design or your own design.
To modify and vary the transactions sent to the example endpoint design or your own design, please refer to section 13.3. Avalon-MM Test Driver Module of the Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide.
Due to an update to the IP Core, the correct filename to be modified has changed from altpcietb_bfm_driver_avmm.v, as stated in the documentation, to altpcietb_bfm_driver_downstream.v.
The information in the Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide has been updated to reflect this change.